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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 5.0 V ≤ V+ ≤ 28 V and -40 ° C ≤ T A ≤ 125 ° C unless otherwise noted. Typical values
noted reflect the approximate parameter mean at T A = 25 ° C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
TIMING CHARACTERISTICS
PWM Frequency (24)
f PWM
–
10
–
kHz
Maximum Switching Frequency During Active Current Limiting
(25)
f MAX
–
–
20
kHz
Output ON Delay (26)
t D (ON)
μ s
V+ = 14 V
Output OFF Delay (26)
V+ = 14 V
t D (OFF)
–
–
–
–
18
18
μ s
,
I LIM Output Constant-OFF Time for Low-Side MOSFETs
I LIM Blanking Time for Low-Side MOSFETs (29) , (28)
(27) (28)
t A
t B
15
12
20.5
16.5
26
21
μ s
μ s
Output Rise and Fall Time (30)
t F , t R
μ s
V+ = 14 V, I OUT = 3.0 A
2.0
5.0
8.0
Disable Delay Time (31)
t D (DISABLE)
–
–
8.0
μ s
Power-ON Delay Time
(32)
t POD
–
1.0
5.0
ms
Wake-Up Delay Time (32)
t WUD
–
1.0
5.0
ms
Output MOSFET Body Diode Reverse Recovery Time
(33)
t RR
100
–
–
ns
Notes
24 The outputs can be PWM-controlled from an external source. This is typically done by holding one input high while applying a PWM
pulse train to the other input. The maximum PWM frequency obtainable is a compromise between switching losses and switching
frequency. See Typical Switching Waveforms, Figures 12 through 19 , pp. 14– 17.
25 The Maximum Switching Frequency during active current limiting is internally implemented. The internal current limit circuitry produces
a constant-OFF-time pulse-width modulation of the output current. The output load’s inductance, capacitance, and resistance
characteristics affect the total switching period (OFF-time + ON-time) and thus the PWM frequency during current limit.
26 Output Delay is the time duration from the midpoint of the IN1 or IN2 input signal to the 10% or 90% point (dependent on the transition
direction) of the OUT1 or OUT2 signal. If the output is transitioning HIGH-to-LOW, the delay is from the midpoint of the input signal to
the 90% point of the output response signal. If the output is transitioning LOW-to-HIGH, the delay is from the midpoint of the input signal
to the 10% point of the output response signal. See Figure 6 , page 12 .
27 I LIM Output Constant-OFF Time is the time during which the internal constant-OFF time PWM current regulation circuit has tri-stated
the output bridge.
28 Load currents ramping up to the current regulation threshold become limited at the I LIM value. The short circuit currents possess a di/dt
that ramps up to the I SCH or I SCL threshold during the I LIM blanking time, registering as a short circuit event detection and causing the
shutdown circuitry to force the output into an immediate tri-state latch-OFF. See Figures 10 and 11 , page 13 . Operation in Current Limit
mode may cause junction temperatures to rise. Junction temperatures above ~160 ° C will cause the output current limit threshold to
progressively “fold back”, or decrease with temperature, until ~175 ° C is reached, after which the T LIM thermal latch-OFF will occur.
Permissible operation within this fold-back region is limited to nonrepetitive transient events of duration not to exceed 30 seconds. See
Figure 9 , page 12 .
29 I LIM Blanking Time is the time during which the current regulation threshold is ignored so that the short-circuit detection threshold
comparators may have time to act.
30 Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal. See Figure 8 , page 12 .
31 Disable Delay Time is the time duration from the midpoint of the D (disable) input signal to 10% of the output tri-state response. See
Figure 7 , page 12 .
32 Parameter has been characterized but not production tested.
33 Parameter is guaranteed by design but not production tested.
33887
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
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